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Compilation of logic equations and logic circuits. Drafting of algorithm of functioning of WFP

Compilation of logic equations and logic circuits. Drafting of algorithm of functioning of WFP 

The stages of building logic circuits.

If the experience of building (synthesis) logic developer small, it is possible to recommend following sequence of actions.

Stage 1. The drawing up truth tables. The most difficult, but very common in practice, the way the schema is the explanation of its work on the conceptual level in the form of set phrases of ordinary language (for example, Russian). The difficulty of the stage stand’is related to the fact, the task describes informal terms, that allows for an ambiguous interpretation of its. The main objective of phase - formalization of the problem, in the process which you need to consider the value of the function for each combination of argument values, if you need to supply to the customer clarifying questions. The result of step - the truth table. This task, ambiguous interpretation of which is impossible. The most difficult bugs arise at the stage of formalization. Only if the table due to the significant number of variables is too cumbersome or if the function is simple, familiar and its meaning is quite clear, you can directly start with writing of an analytical formula.

Stage 2. If the function is not defined on all sets of arguments, we need to eliminate the ambiguity table. When there are few null values, it is better to consider several options. If the number of values or indifferent, or the case great, it, possible, have feature or all zeros, or all units - so, in order to reduce the number of members DDP direct function or its inverse.

Stage 3. Fully on a particular table to be DNF. If we consider several variants of regularization or if there is hope, the inversion function will be realized better, further work will involve several options GDNF.

Stage 4. To minimize DNF by any means. At this stage, sometimes the resolution, to stop searching for the best option (which, possible, and there is no).

Stage 5. To implement the obtained diz’junction forms the logical basis for a given series of elements. To try options for implementation on And-OR-NOT and and-NOT, AND NOT.

Stage 6. To evaluate the dual variant of the logical framework to reflect changes in the number of input and output inverters.

Stage 7. To try to find a decomposition of the function, to each fragment of the obtained decomposition depended on a smaller number of arguments, than the initial function. To try it different ways. 

Stage 8. Choose from obtained in stages 5,6,7 the most suitable variants from the point of view of a goal.  

Usually experience these stages begin mutually to penetrate each other, some stages are omitted entirely, more and more assessments are carried out very quickly, almost on an intuitive level, and drafting of logic circuits becomes interesting, even gambling. 

Creation of logic equations begins with learning the task, determine the number of operands, what are you going to participate in the work of the microcontroller. Define the basic logical operations between operands, then all operands to a single value, minimizing the equation, if possible. The calculation of the logical equation, that is, meet or do not meet the results targets of the task.

Drafting of algorithm of functioning of WFP

The algorithm of operation of WFP shall be determined in accordance with the requirements of the task and determines the development of functional circuits WFP.

For all devices there is a mode cold start.

Cold start. While power on -5V; +5In and 12V (or sequentially in the specified order) and applying clock pulses to the microprocessor of the generator of clock intervals. 

All registers and flags are set in MP custom statuses. After that is served from the GTI to the RESET input of the MP signal of a high level of at least 3 cycles - the counter (PC), trigger resolution interrupt (the output of the INTE), and the trigger confirmation capture (output HLDA) reset, and the microprocessor begins fetching from the memory commands, placed with a zero address.

Depending on the commands that MP passes through a sequence of different machine cycles, have the appropriate number of clock cycles. So, as a result of executing the HLT command is programmed to transition to the “stopping”state. The work status of GPS “expectations” is intended to align its work with existing slow memory or peripherals is determined by the level of the input signal READY at the input of the MP and the output WAIT. The high signal on the HOLD input of the MP switches to “capture”. 

Then the control signals on the findings of the MP do not change, however, the findings of the data bus and address go into the state visokoye. This state is intended, to the external device can write or read data directly to the system memory, bypassing the microprocessor. The mode “capture” significantly increases the speed of information exchange, that is determined by the initiative of an external device. Able to “break” the MP is subject to receipt of the input signal of high level INT, periodically checked by MP at the last step of the command execution. An interrupt request can be executed, if a trigger interrupt MP (the output of the INTE) set to “1”. At the beginning of this trigger on the RESET signal reset to “0” . Allow interrupt it is possible programmatically using the team EI. For the transition routines for handling interrupts can be used commands RST N or CALL. 

The block diagram of algorithm of functioning of WFP should include the initial start-up, after which initializes the respective elements of a microprocessor system. Also in the block diagram includes the modes of reading and recording information from ADCS and DACS, program execution processing, which is determined by the equation of digital filter and other appropriate actions.

The input ADC can be implemented in one of two ways:

• software survey, in which the initiator of the exchange is a microprocessor, periodically polls the data ready;

• in interrupt mode, wherein the data generates an interrupt signal to the MP, resulting in MP goes to the subroutine interrupt processing ( input from ADC).

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