-To print this articleOrganization pam’CPU
Organization pam’for
As indicated, Intel8086(88) has pam’Yat 1 MB. For, to perform the addressing for such a large number of cells, you must have 20-bit pointer. Because the instruction pointer IP (like other registers MP has 16 discharges, the MP does not have direct access to all memory. This task is solved by segmenting the pam’for, that is, of its division into parts. Organization segment
The division is made so, each segment contains up to 64 KB (65 536 bytes). The start address can be set by software and must always start with a 16-byte boundaries. Recall, the exchange of information between the MP and pam’s memory takes place using physical addresses.
The program often uses logical addresses, that allows you to record commands without pre-defining places, where this command will be located at pam’for. A logical address has two components: segment base and offset values within the segment. Once the interface unit accesses the pam’for, adder address (The AGR) generates the physical address according to the rule: the value base of the segment is shifted four digits to the left and received 20-bit number is added to the offset.
The base address of the segment obtained by dividing the physical address of the starting cell of a segment on 16. These addresses are contained in segment registers (so, MP 8086 can simultaneously serve up to four segments). The location of the segment overlaps with only one restriction: it needs to be on the verge of sixteen bytes (i.e., the physical address of a start cell must be divisible by 16).
If the segment in a certain way a certain, the registers pointers can be used to address access any byte or word within this segment. So, The PM has access only to 64 KB pam’for, while addressing to 1 MB is only possible with the use of segment registers. This is one of the drawbacks of the seven MP’th 8086 (88). For example, MP Motorola MS 68000 (contains 32-bit registers-pointers) can directly address up to 16 MB pam’for. SS
As stated above, MP has four register segments. So, at the same time there are four segments addressed :
• team CS;
• data DS;
• additional ES;
• stack SS.
The segments can be adjacent (And, With), divided (With, E), to overlap partially (In, D; E, G) or completely (And, In or E, F).
Command segment contains the machine instructions, who selects the device SV’communication, and performs execution unit.
The data segment is used for hard’'yatovuvannya programs, variable and fixed.
The overlay provides additional 64 KB working memory’for.
Stack segment contains a stack structure with a capacity of up to 64 KB.
If all the registers segments to load the same base address, all four segments will reflect the same region of physical memory.
Cache-pam’Yat
To increase performance when handling the processor operative to pam’memory architecture 32-bit processors are implemented as a hierarchy of pam’for, which suggests the presence of relatively large capacity and low speed dynamic DRAM (Dynamic RAM) the smaller capacity and more performance cache-a pam’for, SRAM or static (Static RAM),
The term “cache” (cache) in our case, corresponds to the value “cache” and the secret of the hiding place is, a special controller cache may include use of the processor specific part of the operational pam’s memory and download it in high speed cache- pam’Yat. In modern computer’computers cache-pam’Yat is based on two- or three-level scheme. The first-level cache (LI Cache) built directly into the chip core is a microprocessor, since i486. The second-level cache (L2 Cache) installed on the motherboard and joined a special internal processor bus. Starting with the P6 CPU secondary cache are mounted in the housing of the microprocessor. The capacity of the cache reaches the highest levels of hundreds of MB, and performance is roughly half the cache of the first level. The tertiary cache installed on the motherboard, or in the case of the microprocessor (used when building the server and cluster systems).
A caching pam’s memory in a personal computer’cars
By definition, cache-a pam’Yat have lesser capacity, than operational, consequently cannot keep a copy of all operational pam’for. This type of pam’memory stores only a limited amount of information and table (list) the data fit the main parts pam’for. In addition, not all operative pam’Yat, which is available to the processor, can be cached. The main reason for this is the possibility of controller cache.
The performance of the cache’s memory obviously depends on, how well are data in, in which there swennen. of CPU. There are two cases:
• if the result of the application processor to the cache found the corresponding.
Vienna data, pre-fetched from the underlying pam’for, we believe, there was a cache hit (cache hit);
• if the result of the application processor's data cache was not then believe that there has been a cache miss (cache miss). In this case, the processor needs to read data from the main pam’for.
Indesenna the number of cache hits to the total number of accesses is called the hit ratio, or success. The percentage of successful hits mainly depends on the caching algorithm of the data blocks of the main pam’s memory to the cache.
The cache controller provides the data transmission lines of a certain length (cache line). Each cache line corresponds to a specific block of data basic pam’s memory, and the address information of the data copied to it and its condition. If in the current time line reflects accurate information, such a string is called valid (valid), otherwise - invalid. Information about data block address or page number and the position of the line is called the tag (tag) and stores in it’'yazanyy with the given string, the special cell of memory’s for the tags (tag RAM). The variant sektorowego cache, in which one row contains information about a number of adjacent cells (sectors).
There are two policies or strategies of the writing data from the cache in RAM pam’Yat: write-through WT (Write Through) and write-back WB (Write Back). Write-through involves the execution of each write operation to both the cache line and operational pam’Yat. This strategy was used in the first i486 processors. In modern processors is dominated strategy writeback, the essence of which is to reduce the number of write operations on the system bus main memory’for.
Depending on the display unit main memory’s memory for a cache line, there are three types of architecture cache-a pam’for:
• direct-mapped cache (direct-mapped cache);
• fully associative cache (fully associative cache);
• dial-associative cache (set-associative cache).
Stack - this is a special area of memory’for. In addressing this field manages the register or the stack pointer SP. Use this pam’Yat primarily for temporary storage of register contents. It is temporary. The most important thing to understand, how does the stack. And it works on the principle of first come last gone. Let's imagine. I lay the book on the table. Then on top of another book. The first book below. What would get her first I need to remove the top and only then I get access to the first. But you can just her in my life to pull. Can. Imagine a bunch of books to the ceiling. Try to pull lower. There is a huge chance that You these books and fill up.